1. Field of the Invention
The invention relates to a semiconductor device having an insulated gate electrode, and further to a method of fabricating the same.
2. Description of the Related Art
FIG. 1 illustrates a conventional MOSFET formed at a surface thereof with a U-shaped recess.
The illustrated MOSFET includes an n.sup.+ semiconductor substrate 1, on which an n.sup.- epitaxial layer 2 is formed. The n.sup.- epitaxial layer 2 is formed at a surface thereof with a p-type base region 3, at a surface of which is formed an n.sup.+ source region 4. The n.sup.- epitaxial layer 2 other than the p-type base region 3 constitutes a drain region 2a.
The n.sup.- epitaxial layer 2 is formed with a U-shaped recess 5 starting from a surface of the source region 4 and reaching the drain region 2a through the base region 3. The recess 5 and a part of the source region 4 are covered with a gate oxide film 6, on which a gate electrode 7 is formed. An interlayer insulating film 8 is formed on the gate electrode 7 and the gate oxide film 6 so that the gate electrode 7 is entirely covered with the interlayer insulating film 8. The source region 4 and the base region 3 make electrical contact with a source electrode (not illustrated) at a surface of the base region 3 and also at a portion of a surface of the source region 4 on which the interlayer insulating film 8 is not formed.
A method of fabricating the above-mentioned conventional MOSFET is explained hereinbelow with reference to FIGS. 2A to 2C.
As illustrated in FIG. 2A, the n.sup.- epitaxial layer 2 is formed in the n.sup.+ semiconductor substrate 1. Then, a silicon dioxide film 10 is formed at a surface of the epitaxial layer 2 by thermal oxidation, and a silicon nitride film 11 is formed all over the silicon dioxide film 10 by chemical vapor deposition (CVD). The silicon nitride film 11 acts as a mask for preventing growth of the silicon dioxide film 10. Thereafter, the silicon nitride film 11, the silicon dioxide film 10, and the epitaxial layer 2 are etched at a selected region by photolithography and dry etching to thereby form a recess 5.
Then, as illustrated in FIG. 2B, the recess 5 is thermally oxidized to thereby form LOCOS oxide film 13 in the recess 5. At the same time, the rectangular recess 5 is changed into a U-shaped recess. Then, the silicon nitride film 11 is completely removed by wet etching. Then, the semiconductor substrate 1 is ion-implanted with boron with LOCOS dioxide film 13 being used as a mask, followed by annealing for thermal diffusion of boron to thereby form the p-type base region 3 in the epitaxial layer 2.
Then, arsenic is ion-implanted into the base region 3 with both LOCOS dioxide film and a photoresist film (not illustrated) being used as a mask, followed by annealing for thermal diffusion of arsenic to thereby form the n.sup.+ source region 4. The epitaxial layer 2 other than the base region 3 and the source region 4 constitutes the n.sup.- drain region 2a.
Then, as illustrated in FIG. 2C, LOCOS oxide film 13 and the silicon dioxide film 10 are removed by wet etching to thereby expose the base region 3, the source region 4, and the recess 5. Then, a gate oxide film 6 is formed on both an inner wall of the recess 5 and surfaces of the base region 3 and the source region 4 by thermal oxidation. A polysilicon layer 15 is formed all over the epitaxial layer 2 by CVD.
Then, as illustrated in FIG. 1, the polysilicon film 15 is patterned by photolithography and dry etching so that the polysilicon film 15 remained unetched only in the recess 5 and on a part of surface of the source region 4, to thereby form the gate electrode 7. Thereafter, the epitaxial layer 2 is covered at a surface thereof with the interlayer insulating film 8 by CVD.
Then, there is formed a contact in the interlayer insulating film 8 and the gate oxide film 6 so that a surface of the base region 3 and a part of a surface of the source region 4 are exposed. Then, the epitaxial layer 2 is entirely covered with an aluminum film by sputtering, followed by removal of the aluminum film in a selected region by photolithography and dry etching, to thereby form a source electrode (not illustrated) which makes electrical contact with both the base region 3 and the source region 4.
In the above-mentioned method, it is necessary to carry out steps of photolithography and etching for forming the gate electrode 7 of the polysilicon film 15 and also for making a contact between the source electrode and the source region 4. Hence, it is also necessary to have a registration margin for a photoresist mask when the above-mentioned photolithography steps are carried out. This causes a problem that it is quite difficult to form the source region small.
Japanese Unexamined Patent Publication No. 4-258174 published on Sep. 14, 1992 has suggested a semiconductor device including a semiconductor substrate formed at a surface thereof with a trench recess, a gate oxide film covering inner and bottom walls of the recess therewith, a first polysilicon film formed in the trench recess, and a second polysilicon film surrounded by the first polysilicon film for planarizing the trench recess, and an oxide film formed only on a gate electrode for electrically insulating the first polysilicon film from source region.
However, the method suggested in the above-mentioned Publication has the same problem as mentioned above. That is, it is quite difficult to form a source region smaller because of necessity of a registration margin for a photoresist mask.